1. Field of the Invention
The invention generally relates to computer data transfer, and more particularly relates to a direct memory access (DMA) transfer.
2. Prior Art
In direct memory access (DMA) transfers, a special control circuit is provided to enable transfer of a large block of data directly between the device and the main memory without incurring excessive overhead by the CPU. The CPU still sets up the transfer by sending initialization information namely the starting address in memory, the data, and the number of words to be transferred to the DMA engine. However, subsequent to this, the DMA engine controls the actual data transfer.
Generally, the steps in the execution of a data transfer using DMA are as follows:
1. Upon being interrupted by the DMA controller, the CPU loads the DMA controller with a starting address for the memory transfer and the number of words to be transferred. PA1 2. When the source device has the data ready to be transferred to the memory or when the destination device is ready for the transfer from the memory, the DMA controller sends a DMA request to the CPU. PA1 3. The CPU acknowledges the DMA request, gives up the control of its address and data bus and appropriate control lines, and suspends any processing that requires use of the address and data bus. PA1 5. When the required number of words has been transferred, the DMA controller terminates the DMA request and interrupts the CPU to indicate that the DMA transfer is complete.
4. The DMA controller provides an address and control signals to read or write. The source/destination device provides or accepts the data on the bus. After a data byte/word is transferred, the DMA controller increments its address register and decrements its word count register. The DMA controller repeats this step if the required number of words has not been transferred.
As discussed above, each DMA data transfer involves only one read or write transaction along with the starting address and byte/word count.
Graphic and video image processing in computer systems often involves heavy data transfer. A graphic or video image is made up of large blocks of pixels which translate into even larger blocks of data bytes. After graphic and video images enter a computer system through video ports, network ports, and mass storage devices such as CD-ROM, they are stored in a system/main memory. Graphic and video images are then transferred to a designated location, usually a local memory inside the graphics/video controller, where image processing is performed. After processing, however, graphics and video image data are transferred back to system/main memory for storage. Because DMA transfer can handle large transfer of data, DMA transfer is the logical method to utilize in moving graphic and video images data in computer systems.
In general, graphics and video image data for a display screen are stored as a bit map in the system memory which promotes ease and efficient display device download. In other words, the system memory is used to hold a bit-per-bit representation of the data being displayed on the monitor. With the resolution and details of graphics and video images constantly improving, the number of bytes/words and hence, the sizes of graphics and video image bitmaps are getting larger. As a result, a large system memory is often required. However, the local memory inside a graphics and video image controller is kept small for economic and technical reasons. For these reasons, graphics and video images are compressed to increase the speed of transfer between the system memory and the local memory.
Briefly, a screen bit map consists of multiple rows of data bytes/words. The number of rows and the number of bytes/words per row depend on the pixel format (e.g., 1024.times.768, 1280.times.1024, etc.) wherein each pixel may be represented by a number of data bytes/words. To reduce the amount of data being transferred, a compression algorithm selects from the screen bit map a block of data that is representative of the screen bit map. The compressed block of data is actually a "small" rectangular area of data from the screen bit map. Although small relative to the screen bit map, the small rectangular area of data consists of multiple rows of multiple words. The compressed block of data is transferred between the system and the local memory. At a later time, the compressed block of data can be later expanded by a decompression algorithm back to the original screen bit map.
Reference is now made to FIG. 1A illustrating, as an example, a 1024.times.768 screen bit map of a graphics/video image in a system memory. The small rectangular area of data representing the compressed block of data can be from any location within the screen bit map. As shown, the small rectangular area of data is located inside the screen bit map. As such, each row of a small rectangular area of data only contains some selected data from a screen bit map row. Hence, the row starting addresses of the small rectangular area of data are not continuous.
Given the amount of data involved in transferring the rectangular area of data, DMA transfer is still desirable. In DMA transferring a rectangular area of data having, for example, eight (8) rows of eight (8) words, eight separate DMA transfers may be required under the prior art due to the incontiguous starting memory addresses of the eight rows. More specifically, for each small rectangular row transfer, the DMA controller needs to interrupt the CPU for each small rectangular row transfer. In response, the CPU needs to provide the DMA controller with the starting system memory address and the number of word/byte count for each small rectangular row transfer. Each time the CPU is interrupted, other on-going or pending tasks are delayed.
Thus, a need exists for a DMA arrangement to transfer a block of data having multiple rows of multiple data bytes from a screen bit map wherein the row starting addresses are not continuous with minimum CPU intervention.